The present invention relates to computer memory systems, and more specifically, to auto-disabling dynamic random access memory (DRAM) error checking based on a threshold.
Double date rate fourth-generation synchronous dynamic random-access memory (DDR4) is a type of dynamic random-access memory (DRAM) that supports a cyclical redundancy check (CRC) on write data that is received at the DRAM from a memory controller. CRC is an error-detecting code that uses a remainder of a polynomial division of a block of data, such as the write data received from a memory controller, to detect accidental changes to the data. The DRAM sends an alert to the memory controller when a CRC error is detected, so that the memory controller can retry the write. A DDR4 also supports parity checking on the command/address bus(ses) between the DRAM and the memory controller. The DRAM sends an alert to the memory controller when a parity error is detected, so that the memory controller can resend the command and/or address.